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%0 Thesis %A Neul, Malte %T Designs and procedures for the characterization of Si/SiGe quantum devices %I RWTH Aachen University %V Dissertation %C Aachen %M RWTH-2025-00316 %P 1 Online-Ressource : Illustrationen %D 2024 %Z Veröffentlicht auf dem Publikationsserver der RWTH Aachen University 2025 %Z Dissertation, RWTH Aachen University, 2024 %X The development of universal quantum computers promises a paradigm shift in problem-solving, with gate-defined single-electron spin qubits in silicon/silicon-germanium (Si/SiGe) heterostructures emerging as promising candidates. Despite their advantageous material properties, such as low spin-orbit coupling and isotropic purification options, these qubits are sensitive to environmental fluctuations, leading to significant inter-device variability. In this thesis, approaches are developed and investigated for characterizing and mitigating this inter-device variability. A systematic measurement method for investigating charging in gated Si/SiGe heterostructures is presented. Through iterative characterization cycles with increasing gate voltages, two distinct charging signatures are defined and the measured stable operation range of 33 devices is compared to simulations. The observations suggest that the stable operating range is primarily limited by the occurrence of equalization paths rather than the density of trap states. An approach for designing new gate layouts based on electrostatic simulations is presented, enabling accurate behavior predictions that are consistent with device measurements. This approach is employed to devise a voltage-line efficient gate layout for mapping charge noise over a large area. Initial measurements of the designed layout underscore the necessity for systematic and automated tuning procedures to ensure time-efficient data generation. Additionally, the relationship between the gate yield and the yield of functioning charge sensors is investigated, showing that a near-perfect gate yield is required to benefit from large devices. The adaptation of a gate layout for industrial fabrication processes is also studied using simulations, which indicate that the device can be operated reliably even when fabrication tolerances are considered. Furthermore, an alternative annealing method based on local laser heating for activating phosphorus-implanted Ohmic contacts is evaluated. Optical calibration studies show laser power as decisive parameter, whereby the power requirement depends primarily on virtual substrate details. A contact resistance of 530 Ω at 4.2 K is achieved for a laser-annealed sample, while a laser-annealed Hall bar exhibits transport properties equal to or superior to a furnace-annealed reference, with an electron mobility of μ = 2.4x105 cm2V-1s-1 at an electron density of n = 5.0x1011cm-2. %F PUB:(DE-HGF)11 %9 Dissertation / PhD Thesis %R 10.18154/RWTH-2025-00316 %U https://publications.rwth-aachen.de/record/1000385