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@PHDTHESIS{Chen:1005699,
author = {Chen, Hsin-Yu},
othercontributors = {Waser, Rainer and Mayer, Joachim},
title = {{R}edox-based random access memory arrays for
computing-in-memory and neuromorphic computing},
volume = {109},
school = {RWTH Aachen University},
type = {Dissertation},
address = {Jülich},
publisher = {Forschungszentrum Jülich GmbH, Zentralbibliothek, Verlag},
reportid = {RWTH-2025-01945},
isbn = {978-3-95806-814-8},
series = {Schriften des Forschungszentrums Jülich. Reihe
Information/information},
pages = {x, 154 Seiten : Illustrationen},
year = {2025},
note = {Abweichender Titel auf dem Buchrücken; Dissertation, RWTH
Aachen University, 2025},
abstract = {The advancement in modern computing technology and
applications strongly relies on the transistor downscaling
that has been following Moore’s law for almost 60 years.
However, the device miniaturization is substantially
approaching its physical limit. The further development of
computation performance requires “more than Moore”
innovations such as memory-centric computing architectures,
which have been proposed to break the von Neumann
bottleneck. Recently, computing-in-memory (CIM), combining
the processor function into the memory and executing
computation directly in the memory, and neuromorphic
computing (NC), using artificial electronic synapses and
neurons to form brain-inspired architectures, have attracted
extensive research interests from academia and industry.
Apart from conventional charge-based memory, redox-based
random access memory (RRAM) has been acknowledged as a
low-cost, high-speed, and non-volatile resistance-based
memory for CIM and NC. Additionally, it has excellent
compatibility to advanced complementary
metal-oxide-semiconductor (CMOS) technology, and also
exhibits ultra-low energy consumption, offering a great
advantage to edge artificial intelligence (AI) applications.
This thesis work focuses on the back-end-of-line (BEOL)
integration and electrical characterization of active RRAM
arrays based on valance change memory. Adopting N-channel
metal-oxide-semiconductor field-effect transistors (MOSFETs)
as selecting components, microscale and nanoscale technology
platforms of active RRAM arrays were developed at the
Helmholtz Nano Facility in Research Center Jülich. On the
one hand, in the microscale technology platform, plug-type
TaOx RRAMs were integrated on the NiSi drain contacts of
planar high-k metal-gate MOSFETs, where the NiSi layer was
not suggested to serve as the bottom electrode of RRAM
directly. In the process of producing contact holes with
areas of 2×2 μm2 to expose the NiSi drain contacts, a
light interference issue was identified in the contact
lithography, and the microloading effect was found
considerable in the reactive-ion-etching (RIE) using CHF3.
Accordingly, a direct writing approach was introduced by
employing a maskless aligner, and the etching time was
prolonged with additional wet etching in 1 $\%$ HF solution.
On the other hand, the nanoscale technology platform is
based on monolithic integration of RRAMs with CMOS circuitry
taped out with TSMC 180 nm technology node. Configured with
64×64 1T-1R arrays, this platform is designed with on-chip
signal amplifiers and driving/sensing circuitry to realize
dot product engines, which serve as brain-inspired
energy-efficient AI accelerators. Using e-beam lithography
(EBL), the N-channel MOSFETs fabricated in the
front-end-of-line were integrated with crossbar RRAM devices
in the BEOL. In the fabrication of nanoscale RRAMs, the
significantly low device yield was attributed to the
redeposition during the Pt etching through Ar
reactive-ion-beam-etching (RIBE), which is also known as
fencing. Consequently, the fence removal was carried out
with an additional CF4 RIBE process at a tilted angle
following after the Ar-based RIBE process. Besides, a
fence-free RIE process with Cr hard masks using a gas
mixture of Cl2 and Ar was developed to avoid significant
fencing during the Ar-based RIBE process. To drive the
RRAM-integrated CMOS die, chip packaging was carried out to
enable the connection to a customized operating hardware.
Eventually, bipolar resistive switching was successfully
performed on the packaged chip, which verifies the
functionality and paves the way to realizing NC
applications. From quasi-static electrical measurements of
the TaOx RRAMs integrated on the established technology
platforms, the 1T-1R configuration was proven advantageous
in improving the current overshoot control, which enables
consistent and reliable switching characteristics, in
comparison to the 1R configuration. In addition, multi-level
resistive switching was demonstrated on 1T-1R unit cells
through modulations of the gate voltage during SET process
and the RESET-stop voltage respectively. In the former case,
when the gate voltage for SET increases, the resistance of
low resistance state (LRS) decreases, and the voltage
required to trigger the subsequent RESET process exhibits a
considerable increase. In the latter case, a higher
RESET-stop voltage results in a higher resistance of high
resistance state (HRS), and therefore a minor increase in
the voltage required to trigger the subsequent SET process.
Notably, a surge of variability in the HRS resistance was
observed as the RESET-stop voltage increases, which appears
to be the limitation for the multi-level resistive switching
modulated by the RESET-stop voltage. Furthermore, the
bipolar resistive switching property was found to be
affected by the gate voltage during electro-forming process,
which determines initial conditions of oxygen vacancy
concentration and conductive filament geometry for
subsequent RESET and SET processes. As the gate voltage for
electro-forming increases, the resistances of LRS and HRS
decrease, and the voltages required for SET and RESET are
lowered simultaneously. It was also found that the
electro-formed condition changed dramatically when the
equivalent current compliance exceeded a critical value.
Using a 1T-nR line array configured with TaOx RRAMs, CIM was
experimentally demonstrated by a stateful logic gate for
material implication (IMP), where the transistor not only
provides flexible tuning of the series resistance by the
gate voltage, but also improves current overshoot control
during SET processes in the RRAMs when performing logic
operations. With the focus on the SET process, impact of
device-to-device (D2D) variability on the IMP stateful logic
operations was investigated. By assigning the RRAM device
with the lower voltage required for SET as the q bit, an
absolute advantage in success rate enhancement was concluded
from experiments, suggesting that the inherent D2D
variability in the RRAM array can be exploited for the IMP
stateful logic operations. Lastly, passive nano-crossbar
arrays of TaOx RRAMs with the device spacing of 70 nm were
fabricated to study the thermal crosstalk effect in
high-density RRAM arrays. In the fabrication, the actual
e-beam exposure area was shrunk to compensate the pattern
enlargement effect caused by the non-ideal undercut of
resist profiles in lift-off patterning and the proximity
effect in EBL. By emulating the scenario of WRITE operations
for SET under the V/2 biasing scheme, the half-selected RRAM
cells adjacent to the fully-selected cell show a high
retention failure rate of 72 $\%$ in average, when they were
originally in the HRS. The average bit-flip probability of
46 $\%$ implies the bias polarity over the half-selected
cell determines the tendency of retention failure leading to
a lower resistance state.},
cin = {611610 / 520000 / 080044 / 080009},
ddc = {620},
cid = {$I:(DE-82)611610_20140620$ / $I:(DE-82)520000_20140620$ /
$I:(DE-82)080044_20160218$ / $I:(DE-82)080009_20140620$},
pnm = {BMBF 16ES1133K - Verbundprojekt: Neuro-inspirierte
Technologien der künstlichen Intelligenz für die
Elektronik der Zukunft - NEUROTEC -, Teilvorhaben:
Forschungszentrum Jülich (16ES1133K) / BMBF 16ES1134 -
Verbundprojekt: Neuro-inspirierte Technologien der
künstlichen Intelligenz für die Elektronik der Zukunft -
NEUROTEC - (BMBF-16ES1134) / BMBF 16ME0399 - Verbundprojekt:
Neuro-inspirierte Technologien der künstlichen Intelligenz
für die Elektronik der Zukunft - NEUROTEC II -
(BMBF-16ME0399) / BMBF 16ME0398K - Verbundprojekt:
Neuro-inspirierte Technologien der künstlichen Intelligenz
für die Elektronik der Zukunft - NEUROTEC II -
(BMBF-16ME0398K) / SFB 917 Z04 - Technologieplattform für
nanoskalige ReRAM- und PCM-Bauelemente (Z04*) (426850996) /
SFB 917: Resistiv schaltende Chalkogenide für zukünftige
Elektronikanwendungen: Struktur, Kinetik und
Bauelementskalierung "Nanoswitches"},
pid = {G:(BMBF)16ES1133K / G:(DE-82)BMBF-16ES1134 /
G:(DE-82)BMBF-16ME0399 / G:(DE-82)BMBF-16ME0398K /
G:(GEPRIS)426850996 / G:(GEPRIS)167917811},
typ = {PUB:(DE-HGF)11 / PUB:(DE-HGF)3},
url = {https://publications.rwth-aachen.de/record/1005699},
}
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