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@PHDTHESIS{Wang:1012236,
author = {Wang, Lantao},
othercontributors = {Heinen, Stefan and Oehm, Jürgen},
title = {{F}requency generation for {ADPLL}s in automotive {FMCW}
radar using nano-scale {CMOS}},
school = {Rheinisch-Westfälische Technische Hochschule Aachen},
type = {Dissertation},
address = {Aachen},
publisher = {RWTH Aachen University},
reportid = {RWTH-2025-04936},
pages = {1 Online-Ressource : Illustrationen},
year = {2025},
note = {Veröffentlicht auf dem Publikationsserver der RWTH Aachen
University; Dissertation, Rheinisch-Westfälische Technische
Hochschule Aachen, 2025},
abstract = {Frequency-modulated continuous-wave (FMCW) radars are
extensively utilized in modern automobiles due to their
capability to measure distance and velocity, thereby
contributing to the reduction of traffic accidents. In these
applications, generating the frequency-modulated (FM) signal
commonly involves the use of a phase-locked loop (PLL).
Traditional charge-pump analog PLLs, however, suffer from
several drawbacks, including a large silicon footprint
caused by the bulky passive loop filter and the significant
contribution of the charge-pump to in-band phase noise.With
advancements in technology, designing analog PLLs has become
increasingly challenging due to reduced voltage headroom,
lower quality factors of passive components, and increased
flicker noise from active devices. To address these issues,
the concept of the all-digital PLL (ADPLL) has been
introduced. ADPLLs utilize a digital loop filter that can be
synthesized with standard cells, eliminating the need for a
large analog loop filter, thus reducing silicon area and
costs. Additionally, ADPLLs offer the flexibility to adjust
PLL parameters, such as loop bandwidth, post-fabrication,
making them adaptable to various scenarios. They also
leverage the continuous scaling-down of CMOS technology more
effectively.Despite these advantages, ADPLLs place high
demands on the performance of frequency generation circuits.
The digitally controlled oscillator (DCO) plays a critical
role, as it predominantly affects the out-of-band phase
noise of the ADPLL and must have a wide tuning range to
determine the chirp signal bandwidth and influence the
distance measurement resolution of the FMCW radar.
Furthermore, a fine frequency tuning resolution of the DCO
is essential because a coarse resolution introduces
quantization noise, which degrades the phase noise
performance of the PLL. Moreover, the in-band behavior of
the ADPLL is largely determined by the reference frequency,
typically provided by a crystal oscillator. Reducing the
start-up time of the crystal oscillator is also crucial, as
it limits the system's response time.The aim of this
dissertation is hence to explore architectures for frequency
generation circuits, with a primary focus on the design and
implementation of the DCO and the crystal oscillator, along
with their auxiliary circuitry, such as low-noise power
supplies, frequency dividers and buffers, to enhance the
performance of ADPLLs for FMCW radar applications. The
designs have been validated through measurement results from
three 28-nm CMOS silicon prototypes.},
cin = {616110},
ddc = {621.3},
cid = {$I:(DE-82)616110_20140620$},
typ = {PUB:(DE-HGF)11},
doi = {10.18154/RWTH-2025-04936},
url = {https://publications.rwth-aachen.de/record/1012236},
}
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