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@PHDTHESIS{Liu:1017144,
author = {Liu, Xiaohua},
othercontributors = {Waser, Rainer and Gemmeke, Tobias},
title = {{M}emristive arrays for neuromorphic computing
applications},
school = {Rheinisch-Westfälische Technische Hochschule Aachen},
type = {Dissertation},
address = {Aachen},
publisher = {RWTH Aachen University},
reportid = {RWTH-2025-07160},
pages = {1 Online-Ressource : Illustrationen},
year = {2025},
note = {Veröffentlicht auf dem Publikationsserver der RWTH Aachen
University; Dissertation, Rheinisch-Westfälische Technische
Hochschule Aachen, 2025},
abstract = {In recent years, the emergence of general-purpose large
language models (LLM), represented by ChatGPT from OpenAI
and Gemini from Google, has profoundly impacted various
aspects of human society. As a critical foundational
resource for supporting LLM training and inference, the
scale of computing power plays a decisive role in
determining model quality and inference efficiency. However,
the von Neumann bottleneck has become a major obstacle to
enhancing computing power. In the classical von Neumann
architecture, the computing unit and the memory unit are
physically separated. First of all, the performance
improvement of computing units, following Moore's Law,
outpaces that of memory units, leading to an ever-widening
gap in data processing speeds. Secondly, the frequent data
transfer between these units incurs substantial energy
consumption and latency, severely limiting computing
efficiency. To address the von Neumann bottleneck, current
research focuses on two primary directions: one involves
multi-chip stacking technologies, such as high-bandwidth
memory, to shorten data transfer paths; the other draws
inspiration from the human brain to integrate computing and
memory functions, thereby advancing neuromorphic computing
architectures. Neuromorphic computing based on redox-based
resistive random access memory (ReRAM) arrays is regarded as
a promising solution to achieve this goal. As a typical
building block for these arrays, the 1T1R structure has been
widely adopted in neuromorphic computing due to its unique
advantages. Primarily, the transistor functions as a
selector, effectively suppressing sneak-path currents in
passive ReRAM arrays. Secondly, the transistor serves as a
current-limiting device, thereby enabling multi-state
programming of ReRAM cells by adjusting the gate voltage.
However, the transfer characteristics of the transistors are
directly influenced by their channel dimensions, while ReRAM
devices with different material systems impose varying
requirements on the operating current. Thus, in the design
of 1T1R structures, ensuring that the electrical
characteristics of the transistor are well-matched with
those of the ReRAM is of critical importance. In this study,
the electrical performance of 1T1R structures with three
different transistor width-to-length (W/L) ratios was
characterized. By extracting the intrinsic voltage drop and
current relationship of ReRAM devices, the impact of
transistor characteristics on the switching behavior of
valence change mechanism (VCM)-based ReRAM devices was
analyzed. Furthermore, based on the intrinsic switching
properties of ReRAM devices, a method was proposed to
estimate the switching curve under specific transistor and
voltage conditions, providing guidance for designing
transistor dimensions that meet the resistance window
requirements of ReRAM devices. In addition to device design,
programming schemes tailored to the electrical
characteristics of ReRAM devices are also necessary for
different application scenarios. For instance, in the
context of neural networks for analog computing, ReRAM
devices must demonstrate the ability to achieve continuous
multi-level storage. This requires the development of
programming algorithms that leverage the switching kinetics
of ReRAM devices to fully exploit their programmability. In
contrast, for binary neural networks, ReRAM devices must
ensure fast and stable binary-state storage. In the second
part of this study, predefined programming-verify algorithms
were employed to compare the electrical performance of three
different 1T1R structures during the SET process. By
utilizing the JART VCM v1b compact model, the relationship
between voltage parameters and device conductance during the
SET process was systematically analyzed. Additionally, the
effects of pulse width and pulse number on programming
outcomes were investigated, and the short-term instability
of programming results was analyzed to explore optimization
strategies for enhancing programming stability. Furthermore,
the potential sources of instability during the programming
process were examined using three-dimensional Kinetic Monte
Carlo simulation, providing a theoretical foundation for
improving programming schemes for ReRAM devices. Finally,
functional testing of 1T1R arrays was conducted in the
context of vector matrix multiplication (VMM) applications.
The impact of switching voltage parameters on the output
current read margin was analyzed through the
characterization of 1T1R arrays with transistors of
different W/L ratios. The experiments also verified that the
interference effect between adjacent cells in the three 1T1R
structures was negligible. Building on this, an 2 x 2 1T1R
array was used to successfully demonstrate VMM using
pulse-width encoded input signals. Experimental results
indicate that VCM-based 1T1R arrays exhibit significant
potential in neuromorphic computing, providing a viable
technological pathway to overcome the von Neumann
bottleneck.},
cin = {611610},
ddc = {621.3},
cid = {$I:(DE-82)611610_20140620$},
pnm = {BMBF 16ME0398K - Verbundprojekt: Neuro-inspirierte
Technologien der künstlichen Intelligenz für die
Elektronik der Zukunft - NEUROTEC II - (BMBF-16ME0398K) /
BMBF 16ME0399 - Verbundprojekt: Neuro-inspirierte
Technologien der künstlichen Intelligenz für die
Elektronik der Zukunft - NEUROTEC II - (BMBF-16ME0399) /
BMBF 03ZU1106AA - NeuroSys: Memristor Crossbar Architekturen
(Projekt A) - A (03ZU1106AA) / BMBF 03ZU1106BA - NeuroSys:
Skalierbare Photonische Neuromorphe Schaltkreise (Projekt B)
- A (03ZU1106BA)},
pid = {G:(DE-82)BMBF-16ME0398K / G:(DE-82)BMBF-16ME0399 /
G:(BMBF)03ZU1106AA / G:(BMBF)03ZU1106BA},
typ = {PUB:(DE-HGF)11},
doi = {10.18154/RWTH-2025-07160},
url = {https://publications.rwth-aachen.de/record/1017144},
}
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