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@MASTERSTHESIS{Baum:1029237,
      author       = {Baum, Martin},
      othercontributors = {Noll, Thomas and Bluhm, Jörg},
      title        = {{H}euristic circuit mapping strategies for the {S}pin{B}us
                      architecture},
      school       = {RWTH Aachen University},
      type         = {Bachelorarbeit},
      address      = {Aachen},
      publisher    = {RWTH Aachen University},
      reportid     = {RWTH-2026-02163},
      pages        = {1 Online-Ressource : Illustrationen},
      year         = {2026},
      note         = {Veröffentlicht auf dem Publikationsserver der RWTH Aachen
                      University 2026; Bachelorarbeit, RWTH Aachen University,
                      2025},
      abstract     = {Running quantum programs on real hardware requires a
                      compilation process in which qubit operations must be mapped
                      onto physical resources, a task commonly referred to as the
                      mapping problem. The objective is to choose a mapping that
                      minimizes the execution time of the compiled program. This
                      is critical because qubits are susceptible to decoherence,
                      which limits the time available for computation. This thesis
                      introduces an algorithm for addressing the mapping problem
                      on the SpinBus architecture, a shuttling-based platform in
                      which qubits can physically move and where certain types of
                      conflicts must be considered. Because the mapping problem is
                      believed to be computationally hard, our approach relies on
                      heuristic strategies that do not guarantee optimality but
                      produce high-quality solutions within practical time limits.
                      We also develop a method for generating an initial qubit
                      placement. We evaluate the proposed methods on a suite of
                      benchmark circuits and compare them to a baseline mapping
                      strategy. Our evaluation considers several metrics that
                      capture the runtime of the mapping algorithm, the total
                      amount of required shuttling, the likelihood of conflicts,
                      and the achievable parallelism.},
      cin          = {121310},
      ddc          = {004},
      cid          = {$I:(DE-82)121310_20140620$},
      typ          = {PUB:(DE-HGF)2},
      doi          = {10.18154/RWTH-2026-02163},
      url          = {https://publications.rwth-aachen.de/record/1029237},
}