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%0 Thesis
%A Lanius, Christian Dominik
%T Design of digital compute-in-memory architectures for efficient hardware systems
%I Rheinisch-Westfälische Technische Hochschule Aachen
%V Dissertation
%C Aachen
%M RWTH-2026-03034
%P 1 Online-Ressource : Illustrationen
%D 2026
%Z Veröffentlicht auf dem Publikationsserver der RWTH Aachen University
%Z Dissertation, Rheinisch-Westfälische Technische Hochschule Aachen, 2026
%X Since the advent of large-scale integration, device count and circuit complexity in digital chips have grown exponentially, fueling the digitalization of everyday life. This progress has been enabled by advances in semiconductor fabrication, digital design automation, and system design that exploit increasing compute capability. However, many advances target the processing side, while memory throughput and latency have not scaled commensurately. Massively parallel workloads therefore encounter the memory bottleneck inherent in von Neumann and related architectures, motivating compute-in-Memory (CIM) architectures. In CIM, compute elements are co-integrated with memory cells to alleviate data-movement overheads. This thesis develops an efficient design methodology for CIM architectures, addressing gaps in traditional digital design flows. We evaluate the effectiveness of CIM arrays in genome alignment and deep packet inspection using fabricated silicon. Finally, we develop systems to measure the fabricated designs and assess the impact that these hardware accelerators have on genome alignment in both edge and high-performance contexts. Conventional digital implementation flows start from a hardware description languages (HDL) description, synthesize it to logic gates, and then automatically place and route them, minimizing manual effort but limiting control over cell selection, placement, and regularity. To regain this control, we propose in Chapter 3 a hierarchical approach that defines arrays of standard cells assembled into dense, highly regular arrays [1]. We complement this with a template-based, regular routing scheme that provides the additional regularity required because commercial routers cannot route extremely dense designs. For delay-variation-sensitive applications such as time-domain computing, this approach affords the control needed to mitigate the impact of irregular routing. The methodology produces the design collateral needed for standard implementation flows, allowing seamless integration into the flow, as well as the physical layout. Using this approach, we achieve utilizations above 90
%F PUB:(DE-HGF)11
%9 Dissertation / PhD Thesis
%R 10.18154/RWTH-2026-03034
%U https://publications.rwth-aachen.de/record/1030465