32 Hohenauer, Manuel Leupers, Rainer 611920 Publikationsserver der RWTH Aachen University Aachen English XII, 192 S. : graph. Darst. Over the past few years, the ever increasing complexity and performance requirements of new wireless communications, automotive and consumer electronics applications are changing the way embedded systems are designed and implemented today. The current trend is towards programmable System-on-Chip platforms in order to improve the design efficiency and reduce the risk and costs of hardware redesign cycles. An increasing number of such systems employ Application Specific Instruction-set Processors (ASIPs) as building blocks due to their balance between computational efficiency and flexibility. Consequently, more and more commercial platforms are available for ASIP architecture exploration and design. These platforms comprise retargetable software development tools (C-compiler, assembler, linker, simulator etc.) that can be quickly adapted to varying target processor configurations. Such tools are usually driven by a processor model given in a dedicated Architecture Description Language (ADL). Advanced ADLs are even capable of generating the system interfaces and a synthesizable hardware model from the same specification. The most challenging task designing an ADL, though, is to capture the architectural information needed for the tool generation in an unambiguous and consistent way. This is particularly difficult for compiler and simulator as they essentially need both the information about the instruction's semantics but from different points of view. The compiler, more specifically the compiler's code selector, needs to know what an instructions does in order to select appropriate instructions for a given piece of source code, while the simulator needs to know how the instruction is executed. In practice it is quite difficult, if not impossible, to derive one information from the other. None of the existing ADLs - if compiler generation is supported at all - solves this problem in a sophisticated manner. Either redundancies are introduced or the language's flexibility is sacrificed. Another challenge in this context is retargetable compilation for high-level programming languages like C/C++. Meanwhile, compilers became a necessity in order to attain high software development productivity and to cope with the ever growing complexity of today's applications. Retargetable C compilers however, are often hampered by their limited code quality as compared to hand-written compilers or assembly code since there is usually a trade-off between the compiler's flexibility and the quality of compiled code. In order to narrow the code quality gap this demands flexible retargetable optimization techniques for common architectural features which can be quickly adapted to varying target processor configurations. This thesis presents a novel technique for extracting the code selector description fully automatically from ADL processor models. The approach is based on the Language for Instruction Set Architectures (LISA) ADL using a language extension for instruction semantics description. This enables the automatic generation of C compilers from a LISA processor description without loosing flexibility or introducing inconsistencies. In this way, a high speedup in compiler generation is achieved, that contributes to a more efficient ASIP design flow. The feasibility of the approach is demonstrated for several contemporary embedded processors. Furthermore, two popular architectural classes are selected which demand for specific code optimization techniques, namely processors equipped with SIMD instructions and those with Predicated Execution support. This thesis implements these specific techniques such that retargetability and high code quality within the given processor class are obtained. Moreover, to ease the manual creation of dedicated optimizations on the assembly level, this thesis implements a new retargetable assembler which provides an application programmer interface for user defined code optimizations like e.g. a peephole optimizer. Zsfassung in dt. und. engl. Sprache ; Aachen, Techn. Hochsch., Diss., 2009 ; PUB:(DE-HGF)11, ; 2, ; Anwendungsspezifischer Prozessor SIMD COSY <Compiler-Compiler> Dissertation / PhD Thesis 2009 RWTH-CONV-113549 2009 https://publications.rwth-aachen.de/record/51237