000722029 001__ 722029 000722029 005__ 20251028174652.0 000722029 0247_ $$2ISBN$$a978-1-5090-6036-8 000722029 0247_ $$2ISBN$$a978-1-5090-6037-5 000722029 0247_ $$2ISBN$$a978-1-5090-6038-2 000722029 0247_ $$2ISSN$$a2327-8226 000722029 0247_ $$2WOS$$aWOS:000427098100026 000722029 0247_ $$2doi$$a10.1109/NANOARCH.2017.8053707 000722029 0247_ $$2SCOPUS$$aSCOPUS:2-s2.0-85034737938 000722029 037__ $$aRWTH-2018-223343 000722029 041__ $$aEnglish 000722029 1001_ $$0P:(DE-82)019112$$aHeittmann, Arne$$b0$$eCorresponding author$$urwth 000722029 1112_ $$a2017 IEEE/ACM International Symposium on Nanoscale Architectures$$cNewport, RI$$d2017-07-25 - 2017-07-26$$gNANOARCH$$wUSA 000722029 245__ $$aMixing circuit based on neural associative memories and nanoelectronic 1S1R cells$$honline, print, data medium 000722029 260__ $$aPiscataway, NJ$$bIEEE$$c2017 000722029 29510 $$aProceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH'17) : 25-26 July 2017, Newport, USA / symposium sponsors: IEEE, Association for Computing Machinery, IEEE Computer Society 000722029 300__ $$a119-124 000722029 3367_ $$033$$2EndNote$$aConference Paper 000722029 3367_ $$0PUB:(DE-HGF)7$$2PUB:(DE-HGF)$$aContribution to a book 000722029 3367_ $$0PUB:(DE-HGF)8$$2PUB:(DE-HGF)$$aContribution to a conference proceedings$$bcontrib$$mcontrib 000722029 3367_ $$2BibTeX$$aINPROCEEDINGS 000722029 3367_ $$2DRIVER$$aconferenceObject 000722029 3367_ $$2DataCite$$aOutput Types/Conference Paper 000722029 3367_ $$2ORCID$$aCONFERENCE_PAPER 000722029 500__ $$aDatenträger: USB-Stick 000722029 588__ $$aDataset connected to CrossRef Conference 000722029 591__ $$aGermany 000722029 7001_ $$0P:(DE-82)012360$$aNoll, Tobias G.$$b1$$eCorresponding author$$urwth 000722029 909CO $$ooai:publications.rwth-aachen.de:722029$$pVDB 000722029 9101_ $$0I:(DE-588b)36225-6$$6P:(DE-82)012360$$aRWTH Aachen$$b1$$kRWTH 000722029 9101_ $$0I:(DE-588b)36225-6$$6P:(DE-82)019112$$aRWTH Aachen$$b0$$kRWTH 000722029 9141_ $$y2017 000722029 9151_ $$0StatID:(DE-HGF)0031$$2StatID$$aPeer reviewed article$$x0 000722029 9201_ $$0I:(DE-82)611110_20170101$$k611110$$lLehrstuhl für Integrierte digitale Systeme und Schaltungsentwurf$$x0 000722029 961__ $$c2018-04-03T16:49:22.062690$$x2018-04-03T16:49:22.062690$$z2018-04-03T16:49:22.062690 000722029 980__ $$aI:(DE-82)611110_20170101 000722029 980__ $$aUNRESTRICTED 000722029 980__ $$aVDB 000722029 980__ $$acontb 000722029 980__ $$acontrib