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@PHDTHESIS{Meixner:762972,
      author       = {Meixner, Michael},
      othercontributors = {Noll, Tobias G. and Negra, Renato and Gemmeke, Tobias},
      title        = {{A}ccurate power estimation of deep-submicron {VLSI}
                      circuits considering delay effects and glitches},
      school       = {Rheinisch-Westfälische Technische Hochschule Aachen},
      type         = {Dissertation},
      address      = {Aachen},
      reportid     = {RWTH-2019-06005},
      pages        = {1 Online-Ressource (94 Seiten) : Illustrationen, Diagramme},
      year         = {2019},
      note         = {Veröffentlicht auf dem Publikationsserver der RWTH Aachen
                      University; Dissertation, Rheinisch-Westfälische Technische
                      Hochschule Aachen, 2019},
      abstract     = {Continuously increasing transistor densities as well as the
                      rising demand for mobile computing performance result in an
                      ever-stronger focus on energy efficiency for integrated
                      circuits. To account for the power consumption as early in
                      the design of digital circuits as possible, accurate
                      approaches towards power estimation are required. The
                      abstraction from physical effects that is required for
                      acceleration of the estimation may cause some factors that
                      influence power consumption to be neglected. One of these
                      effects, which is gaining in influence due to growing
                      process variations, is the increased switching activity due
                      to spurious signal pulses called glitches. These pulses are
                      caused by relative differences of gate delays and cause a
                      significant share of the power consumption in typical
                      digital circuits. Due to the strong dependency on physical
                      circuit characteristics the accurate estimation of glitches
                      as well as their effect on power consumption on higher
                      levels of abstraction is a challenge that could not be
                      solved to this date. In this thesis approaches that increase
                      power estimation accuracy of digital CMOS circuits on
                      selected levels of abstraction are investigated. The two
                      developed power estimation methodologies show distinct
                      approaches to successfully take effects due to gate delays
                      and glitches into account during power estimation and allow
                      significant gains in accuracy.},
      cin          = {611110},
      ddc          = {621.3},
      cid          = {$I:(DE-82)611110_20140620$},
      typ          = {PUB:(DE-HGF)11},
      doi          = {10.18154/RWTH-2019-06005},
      url          = {https://publications.rwth-aachen.de/record/762972},
}