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TY  - THES
AU  - Narimani, Keyvan
TI  - Silicon tunnel FETs for digital and analogue applications
PB  - Rheinisch-Westfälische Technische Hochschule Aachen
VL  - Dissertation
CY  - Aachen
M1  - RWTH-2019-08324
SP  - 1 Online-Ressource (XVI, 108, VI Seiten) : Illustrationen, Diagramme
PY  - 2018
N1  - Veröffentlicht auf dem Publikationsserver der RWTH Aachen University 2019
N1  - Dissertation, Rheinisch-Westfälische Technische Hochschule Aachen, 2018
AB  - As number of transistors per unit area in integrated circuits increases, power dissipation of the chips becomes progressively important. Scaling of supply voltage VDD is an important measure to decrease dynamic Pdynamic and static Pstatic power consumption of integrated circuits. However, considering inherent limitation of MOSFETs, this either leads to low operating current or increased leakage current. The tunnel field effect transistor (TFET) is a promising alternative to go beyond this limitation to operate devices at very small supply voltage VDD due to non-thermal quantum mechanical band to band tunneling as the main carrier transport mechanism compared to thermal emission in MOSFETs.In this work, two different TFET design concepts based on point-tunneling andline-tunneling are investigated. In each case, the tunneling probability is optimized with regard to basic physical relations derived from the WKB approximation of band to band tunneling. The end goals are to achieve higher drive currents at lower supply voltages and subthermal (<60 mV/dec) inverse subthreshold swings. The point tunneling based devices are fabricated as single nanowire gate-all-around TFETsbased on tensile-strained silicon on insulator(sSOI) wafers. The devices are highly scaled and employ high-k HfO2 gate dielectric to achieve optimum electrostatic control over the channel. Moreover, careful adjustments of ion implantation and dopant activation in various settings ensure favorable tunneling junction formation. The optimized device shows superior on-current Ion, Ion/Ioff ratio as well very good average subthreshold swing SSavg. For this device, various analog figures of merits are also presented. Low temperature measurements reveal insights about the limiting effect of trap-assisted-tunneling (TAT) at low gate voltages on performance of the fabricated nanowire TFETs. Parasitic ambipolar behavior which is inherent to TFET operation is suppressed by employing a SiO2 spacer to form a gate-drain underlap, effectively switching off the drain tunneling junction. As a result, the ambipolar behavior of NW TFETs fabricated by this method is completely suppressed, making them suitable for different digital and analog circuit applications. To achieve enhanced subthreshold characteristics, line-tunneling based planar silicon TFETs are designed and fabricated by thinning down the source after implantation and dopant activation to get rid of the end of the range (EOR) damage. Devices fabricated by this method show superior SS of 55mV/dec over two decades of drain current. Complementary single NW TFET inverters with and without ambipolarity are fabricated and compared. It is revealed that the suppression of ambipolarity has a positive effect on noise margin of inverters, where the logic levels match the actual bias points. High temperature stability of two-transistor current mirrors based on nanowire TFETs is also evaluated. The measurements show stable operation of the circuit even at high temperatures when the transistors operate in the BTBT region.
LB  - PUB:(DE-HGF)11
DO  - DOI:10.18154/RWTH-2019-08324
UR  - https://publications.rwth-aachen.de/record/766785
ER  -