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000798343 001__ 798343
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000798343 0247_ $$2CORDIS$$aG:(EU-Grant)863258$$d863258
000798343 0247_ $$2CORDIS$$aG:(EU-Call)H2020-FETOPEN-2018-2019-2020-01$$dH2020-FETOPEN-2018-2019-2020-01
000798343 0247_ $$2originalID$$acorda__h2020::863258
000798343 035__ $$aG:(EU-Grant)863258
000798343 150__ $$aOrigami electronics for three dimensional integration of computational devices$$y2019-10-01 - 2024-03-31
000798343 371__ $$aUniversity of Pisa$$bUniPi$$dItaly$$ehttp://www.unipi.it/$$vCORDIS
000798343 371__ $$aTEKNOLOGIAN TUTKIMUSKESKUS VTT$$bVTT$$dFinland$$ehttp://www.vtt.fi$$vCORDIS
000798343 371__ $$aTU Wien$$bTUW$$dAustria$$ehttps://www.tuwien.ac.at/en/$$vCORDIS
000798343 371__ $$aGESELLSCHAFT FUR ANGEWANDTE MIKRO UND OPTOELEKTRONIK MIT BESCHRANKTERHAFTUNG AMO GMBH$$bAMO GMBH$$dGermany$$ehttp://www.amo.de$$vCORDIS
000798343 372__ $$aH2020-FETOPEN-2018-2019-2020-01$$s2019-10-01$$t2024-03-31
000798343 450__ $$aORIGENAL$$wd$$y2019-10-01 - 2024-03-31
000798343 5101_ $$0I:(DE-588b)5098525-5$$2CORDIS$$aEuropean Union
000798343 680__ $$aIncreasing the integrated circuits complexity by lateral scaling, known as Moore’s law, was the major driving force for the semiconductor industry. Now, after more than 4 decades down scaling is approaching fundamental and also economic limitations, and new solutions for further increasing the transistor count are explored. Utilizing the third dimension in chip architecture is one of the most promising directions. However, current solutions like wafer-to-wafer stacking will only deliver solutions for the short term with maximum some tens of layers on-top of each other’s. 
In the ORIGENAL project we propose a radically new approach to address the challenge of ultra-dense 3D integration of CMOS devices by using a thin-film-transistor (TFT) technology on thin foil substrate and the subsequent topological folding in order to achieve a dense 3D packaging with completely new integration architectures. This radically new approach will enable the stacking of thousands of layers on top of each other’s, each containing state-of-the-art CMOS circuits and thus will provide enough fuel to further increase the transistor count on a chip according to Moore’s law for more than 30 years. In addition, new computing concepts like neuromorphic computing will significantly benefit from the highly interconnected architecture developed in this project.
The proposal focuses on the development of a suitable thin-film-transistor technology on ultrathin-foil, the 3D interconnect and architecture, and the required technology for high precision folding. Achieving the ambitious objectives requires an interdisciplinary approach including contributions from Material science, electrical engineering, mechanical engineering, biology, physics and chemistry.
The proposed forefront research will not only lay the foundations for a new line of technology, but also open up an opportunity to reinforce the technological leadership of European players.
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000798343 909CO $$ooai:juser.fz-juelich.de:880790
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