h1

000800375 001__ 800375
000800375 005__ 20230209043017.0
000800375 0247_ $$2CORDIS$$aG:(EU-Grant)863337$$d863337
000800375 0247_ $$2CORDIS$$aG:(EU-Call)H2020-FETOPEN-2018-2019-2020-01$$dH2020-FETOPEN-2018-2019-2020-01
000800375 0247_ $$2originalID$$acorda__h2020::863337
000800375 035__ $$aG:(EU-Grant)863337
000800375 150__ $$aArchitecting More Than Moore – Wireless Plasticity for Heterogeneous Massive Computer Architectures$$y2019-10-01 - 2023-09-30
000800375 371__ $$aIBM Research GmbH$$bIBM$$dSwitzerland$$ehttp://www.zurich.ibm.com$$vCORDIS
000800375 371__ $$aUniversity of Siegen$$bUniversity of Siegen$$dGermany$$ehttps://www.uni-siegen.de/start/index.html.en?lang=en$$vCORDIS
000800375 371__ $$aUniversitat Politècnica de Catalunya$$bUPC$$dSpain$$ehttp://www.upc.edu$$vCORDIS
000800375 371__ $$aGESELLSCHAFT FUR ANGEWANDTE MIKRO UND OPTOELEKTRONIK MIT BESCHRANKTERHAFTUNG AMO GMBH$$bAMO GMBH$$dGermany$$ehttp://www.amo.de$$vCORDIS
000800375 371__ $$aUniversity of Bologna$$bUNIBO$$dItaly$$ehttp://www.unibo.it/en/homepage$$vCORDIS
000800375 371__ $$aÉcole Polytechnique Fédérale de Lausanne$$bEPFL$$dSwitzerland$$ehttp://www.epfl.ch/index.en.html$$vCORDIS
000800375 371__ $$aRWTH Aachen University$$bRWTH$$dGermany$$ehttp://www.rwth-aachen.de/cms/~a/root/lidx/1/$$vCORDIS
000800375 372__ $$aH2020-FETOPEN-2018-2019-2020-01$$s2019-10-01$$t2023-09-30
000800375 450__ $$aWiPLASH$$wd$$y2019-10-01 - 2023-09-30
000800375 5101_ $$0I:(DE-588b)5098525-5$$2CORDIS$$aEuropean Union
000800375 680__ $$aThe main design principles in computer architecture have shifted from a monolithic scaling-driven approach towards an emergence of heterogeneous architectures that tightly co-integrate multiple specialized computing and memory units. This is motivated by the urgent need of very high parallelism and by energy constraints. This heterogeneous hardware specialization requires interconnection mechanisms that integrate the architecture. State-of-the-art approaches are 3D stacking and 2.D architectures complemented with a Network-on-Chip (NoC) to interconnect the components. However, such interconnects are fundamentally monolithic and rigid, and are unable to provide the efficiency and architectural flexibility required by current and future key ICT applications. The main challenge is to introduce diversification and specialization in heterogeneous processor architectures while ensuring their generality and scalability.

In order to achieve this, the WiPLASH project aims to pioneer an on-chip wireless communication plane able to provide architectural plasticity, reconfigurability and adaptation to the application requirements with near-ASIC efficiency but without any loss of generality. For this, the WiPLASH consortium will provide solid experimental foundations of the key enablers of on-chip wireless communication at the functional unit level as well as their technological and architectural integration. The main goals are: (i) prototype a miniaturized and tunable graphene antenna in the terahertz band, (ii) co-integrate graphene RF components with submillimeter-wave transceivers and (iii) demonstrate low-power reconfigurable wireless chip-scale networks. The culminating goal is to demonstrate that the wireless plane offers the plasticity required by future computing platforms by improving at least one key application (mainly biologically-plausible deep learning architectures) by 10X in terms of execution speed and energy-delay product over a state-of-the-art baseline.
000800375 909CO $$ooai:juser.fz-juelich.de:882822$$pauthority$$pauthority:GRANT
000800375 909CO $$ooai:juser.fz-juelich.de:882822
000800375 970__ $$aoai:dnet:corda__h2020::6b738ca222abfbc72bcedbf37d7d1812
000800375 980__ $$aG
000800375 980__ $$aCORDIS
000800375 980__ $$aAUTHORITY