h1

% IMPORTANT: The following is UTF-8 encoded.  This means that in the presence
% of non-ASCII characters, it will not work with BibTeX 0.99 or older.
% Instead, you should use an up-to-date BibTeX implementation like “bibtex8” or
% “biber”.

@PHDTHESIS{Bengel:969153,
      author       = {Bengel, Christopher Reinhard},
      othercontributors = {Waser, Rainer and Strachan, John Paul},
      title        = {{V}ariability-aware compact modeling of
                      valence-change-mechanism based devices for
                      computation-in-memory},
      school       = {Rheinisch-Westfälische Technische Hochschule Aachen},
      type         = {Dissertation},
      address      = {Aachen},
      publisher    = {RWTH Aachen University},
      reportid     = {RWTH-2023-08986},
      pages        = {1 Online-Ressource : Illustrationen, Diagramme},
      year         = {2023},
      note         = {Veröffentlicht auf dem Publikationsserver der RWTH Aachen
                      University; Dissertation, Rheinisch-Westfälische Technische
                      Hochschule Aachen, 2023},
      abstract     = {Today’s modern society relies on semiconductors for a
                      wide range of fields, especially in the domain of
                      information technology. Advancements there are heavily
                      reliant on performance and efficiency improvements of the
                      underlying hardware, especially memory technologies and
                      processing units. For these two types of technology, most of
                      the performance improvements have been achieved through the
                      miniaturization of their core element, the Metal Oxide
                      Semiconductor Field Effect Transistor (MOSFET). Further
                      miniaturization is however becoming increasingly difficult
                      and expensive, as fundamental physical laws are greatly
                      increasing the challenges for technologists and circuit
                      designers. Another path to increase the performance of
                      computing systems is optimizing their architecture, by
                      further utilizing parallel architectures or by performing
                      computation-in-memory. One proposal for the technological
                      and architectural problems is the usage of resistive
                      switching devices, such as Valence Change Mechanism (VCM)
                      based devices to enable computation in memory. In these
                      devices the information of the cell is stored in the
                      resistance of the cell and can be varied over orders of
                      magnitude in a binary or analog fashion, making them
                      promising candidates for computing applications. Independent
                      of the specifics of the various applications, all
                      applications require a deep understanding of the device
                      behavior and their variability. Furthermore, the impact of
                      these physical properties and the variability on the
                      performance of the applications is important. This thesis
                      investigates the physical modeling, including variability,
                      of filamentary and bipolar switching VCM cells, as well as
                      their applications for Computation-in-Memory. The compact
                      modeling of the device-to-device, cycle-to-cycle and
                      read-to-read variability is verified through extensive
                      experimental investigations considering the cell statistics.
                      The compact model developed in this thesis is shown to be
                      able to describe various filamentary switching VCM systems,
                      such as HfOx, ZrOx and TaOx. Initially, the qualitative
                      behavior could be matched, e.g. for the SET and RESET
                      kinetics as well as for IV measurements. in a second step,
                      the difference between device-to-device and cycle-to-cycle
                      variability could be demonstrated. Finally, the focus was on
                      describing reliability, which is affected by read disturb
                      and read noise. The space of Computation-in-memory
                      applications can be split into logic applications, machine
                      learning accelerators and neuromorphic computing
                      applications. All of these fields will be studied in this
                      thesis. In general, the approach is to start by defining the
                      most important device characteristics for each application
                      and by then showing, that this characteristic or combination
                      of characteristics can be described using the compact model.
                      The applications are then built from the ground up, while
                      respecting lessons learned from the lower detail levels.},
      cin          = {611610},
      ddc          = {621.3},
      cid          = {$I:(DE-82)611610_20140620$},
      pnm          = {MNEMOSENE - Computation-in-memory architecture based on
                      resistive devices (780215) / BMBF 16ME0399 - Verbundprojekt:
                      Neuro-inspirierte Technologien der künstlichen Intelligenz
                      für die Elektronik der Zukunft - NEUROTEC II -
                      (BMBF-16ME0399) / BMBF 16ES1134 - Verbundprojekt:
                      Neuro-inspirierte Technologien der künstlichen Intelligenz
                      für die Elektronik der Zukunft - NEUROTEC - (BMBF-16ES1134)
                      / DFG project 167917811 - SFB 917: Resistiv schaltende
                      Chalkogenide für zukünftige Elektronikanwendungen:
                      Struktur, Kinetik und Bauelementskalierung "Nanoswitches"
                      (167917811) / DFG project 422738993 - SPP 2262: Memristive
                      Bauelemente für intelligente technische Systeme
                      (422738993)},
      pid          = {G:(EU-Grant)780215 / G:(DE-82)BMBF-16ME0399 /
                      G:(DE-82)BMBF-16ES1134 / G:(GEPRIS)167917811 /
                      G:(GEPRIS)422738993},
      typ          = {PUB:(DE-HGF)11},
      doi          = {10.18154/RWTH-2023-08986},
      url          = {https://publications.rwth-aachen.de/record/969153},
}