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@INPROCEEDINGS{Shadmehri:998946,
      author       = {Shadmehri, Seyed Hossein Hashemi and Chakraborty, Supriya
                      and Copetti, Thiago Santos and Vargas, Fabian Luis and
                      Poehls, Letícia Maria Bolzani},
      title        = {{U}nderstanding {T}ransistor {A}ging {I}mpact on the
                      {B}ehavior of {RRAM} {C}ells},
      address      = {[Piscataway, NJ]},
      publisher    = {IEEE},
      reportid     = {RWTH-2024-11760},
      year         = {2024},
      comment      = {2024 IFIP/IEEE 32nd International Conference on Very Large
                      Scale Integration (VLSI-SoC) : 6-9 Oct. 2024 : conference
                      location: Tanger, Morocco / publisher: IEEE},
      booktitle     = {2024 IFIP/IEEE 32nd International
                       Conference on Very Large Scale
                       Integration (VLSI-SoC) : 6-9 Oct. 2024
                       : conference location: Tanger, Morocco
                       / publisher: IEEE},
      month         = {Oct},
      date          = {2024-10-06},
      organization  = {2024 IFIP/IEEE 32. International
                       Conference on Very Large Scale
                       Integration, Tanger (Morocco), 6 Oct
                       2024 - 9 Oct 2024},
      cin          = {611110},
      cid          = {$I:(DE-82)611110_20170101$},
      pnm          = {BMBF 03ZU1106CB - NeuroSys: Algorithm-Hardware Co-Design
                      (Projekt C) - B (BMBF-03ZU1106CB) / BMBF 16ES1134 -
                      Verbundprojekt: Neuro-inspirierte Technologien der
                      künstlichen Intelligenz für die Elektronik der Zukunft -
                      NEUROTEC - (BMBF-16ES1134) / G:(DE-82)BMBF-16ME0398K
                      Verbundprojekt: Neuro-inspirierte Technologien der
                      künstlichen Intelligenz für die Elektronik der Zukunft -
                      NEUROTEC II (BMBF-16ME0398K) / TAICHIP - Boosting TalTech
                      Capacity in Reliable and Efficient AI-Chip Design
                      (101160182)},
      pid          = {G:(DE-Juel1)BMBF-03ZU1106CB / G:(DE-82)BMBF-16ES1134 /
                      G:(DE-82)BMBF-16ME0398K / G:(EU-Grant)101160182},
      typ          = {PUB:(DE-HGF)7 / PUB:(DE-HGF)8},
      UT           = {WOS:001587181500023},
      doi          = {10.1109/VLSI-SoC62099.2024.10767807},
      url          = {https://publications.rwth-aachen.de/record/998946},
}