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A System for Synthesizing Abstraction-Enabled Simulators for Binary Code Verification

; ;

In
2010 International Symposium on Industrial Embedded Systems (SIES 2010) : Trento, Italy, 7 - 9 July 2010 / [University of Trento, Italy; IEEE; IES], Seiten/Artikel-Nr: 118-127

Konferenz/Event:2010 International Symposium on Industrial Embedded Systems , Trento , Italy , SIES 2010 , 2010-07-07 - 2010-07-09

ImpressumPiscataway, NJ : IEEE

Umfang118-127

ISBN978-1-4244-5840-7

Online
DOI: 10.1109/SIES.2010.5551382


Einrichtungen

  1. Lehrstuhl für Informatik 11 (Software für eingebettete Systeme) (122810)
  2. Fachgruppe Informatik (120000)



Dokumenttyp
Contribution to a conference proceedings/Contribution to a book

Format
online, print

Sprache
English

Anmerkung
Peer reviewed article

Externe Identnummern
INSPEC: 11487353
SCOPUS: SCOPUS:2-s2.0-77957550822

Interne Identnummern
RWTH-CONV-190384
Datensatz-ID: 119226

Beteiligte Länder
Germany

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Document types > Events > Contributions to a conference proceedings
Document types > Books > Contributions to a book
Faculty of Computer Science (Fac.9)
Public records
Publications database
120000
122810
 Record created 2013-01-28, last modified 2024-11-06
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