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Efficient ASIC Architecture for Low Latency Classic McEliece Decoding

; ; ;

In
IACR transactions on cryptographic hardware and embedded systems 2024(2), Seiten/Artikel-Nr.:403 - 425

ImpressumBochum : Ruhr-Universität Bochum

ISSN2569-2925

Online
DOI: 10.46586/tches.v2024.i2.403-425


Einrichtungen

  1. RWTH Aachen (hsbk000000)


Thematische Einordnung (Klassifikation)
DDC: 510


Dokumenttyp
Journal Article

Format
online

Sprache
English

Anmerkung
Peer review status of article unknown

Interne Identnummern
RWTH-2026-10492
Datensatz-ID: 1046406

Lizenzstatus der Zeitschrift

 GO

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 Record created 2026-11-08, last modified 2026-11-08
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