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Towards SRAM leakage power minimization by aggressive standby voltage scaling — Experiments on 40nm test chips

; ;

In
2017 IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) : October 23-25, 2017, Cambridge, UK / sponsors: IEEE, IEEE Computer Society, TTTC, TCFT, Cadence Academic Network, Seiten/Artikel-Nr: 1-4

Konferenz/Event:30. IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems , Cambridge , UK , DFT 2017 , 2017-10-23 - 2017-10-25

ImpressumPiscataway, NJ : IEEE

Umfang1-4

ISBN978-1-5386-0361-1, 978-1-5386-0362-8, 978-1-5386-0363-5

Datenträger: USB-Stick

Online
DOI: 10.1109/DFT.2017.8244431


Einrichtungen

  1. Lehrstuhl für Integrierte digitale Systeme und Schaltungsentwurf (611110)



Dokumenttyp
Contribution to a book/Contribution to a conference proceedings

Format
online, data medium, print

Sprache
English

Anmerkung
Peer reviewed article

Externe Identnummern
INSPEC: 17471122
SCOPUS: SCOPUS:2-s2.0-85046041772
WOS Core Collection: WOS:000426958300004

Interne Identnummern
RWTH-2018-221755
Datensatz-ID: 718971

Beteiligte Länder
Germany, Netherlands

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The record appears in these collections:
Document types > Events > Contributions to a conference proceedings
Document types > Books > Contributions to a book
Faculty of Electrical Engineering and Information Technology (Fac.6)
Public records
Publications database
611110
 Record created 2018-03-01, last modified 2022-10-25
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