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Architecture and optimization of associative memories used for the implementation of logic functions based on nanoelectronic 1S1R cells

Heittmann, Arne (Corresponding author)^RWTH* ; Noll, Tobias G. (Corresponding author)^RWTH*

In
Proceedings of the 2018 Design, Automation & Test in Europe (DATE) : 19-23 March 2018, Dresden, Germany / general chair: Jan Madsen, Technical University of Denmark, DK ; DATE 2018 sponsors: European Design and Automation Association, Electronic System Design (ESD) Alliance, IEEE Council on Electronic Design Automation, European Electronic Chips & Systems Design Initiative, ACM Special Interest Group on Design Automation, Russian Academy of Sciences, Seiten/Artikel-Nr: 1496-1499

2018

Konferenz/Event:2018 Design, Automation & Test in Europe Conference & Exhibition , Dresden , Germany , DATE 2018 , 2018-03-19 - 2018-03-23

ImpressumPiscataway, NJ : IEEE

Umfang1496-1499

ISBN978-3-9819263-0-9, 978-3-9819263-1-6

Datenträger: USB-Stick

Online
DOI: 10.23919/DATE.2018.8342250
10.23919/DATE.2018.8342250

Einrichtungen

1. Lehrstuhl für Integrierte digitale Systeme und Schaltungsentwurf (611110)

Dokumenttyp
Contribution to a book/Contribution to a conference proceedings

Format
data medium, online

Sprache
English

Anmerkung
Peer reviewed article

Externe Identnummern
WOS Core Collection: WOS:000435148800281
SCOPUS: SCOPUS:2-s2.0-85048749169

Interne Identnummern
RWTH-2018-225717
Datensatz-ID: 728527

Beteiligte Länder
Germany