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BMBF 03ZU1106CA

NeuroSys: Algorithm-Hardware Co-Design (Projekt C) - A

Grant period2022-01-01 - 2024-12-31
Funding bodyBundesministerium für Bildung und Forschung
 BMBF
Further information: Homepage
IdentifierG:(BMBF)03ZU1106CA

 

Recent Publications

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http://join2-wiki.gsi.de/foswiki/pub/Main/Artwork/join2_logo100x88.png Contribution to a book/Contribution to a conference proceedings  ;  ;  ;  ;
GUPA: Group-Wise Uniform Pruning Accelerator for Depthwise Separable Convolution
2025 IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL CHIPS) : 16-18 April 2025
2025 IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS, TokyoTokyo, Japan, 16 Apr 2025 - 18 Apr 20252025-04-162025-04-18
IEEE () [10.1109/COOLCHIPS65488.2025.11018601]  GO  Download fulltext Files BibTeX | EndNote: XML, Text | RIS

http://join2-wiki.gsi.de/foswiki/pub/Main/Artwork/join2_logo100x88.png Journal Article (Review Article)  ;  ;  ;  ;
Scaling Logic Area With Multitier Standard Cells
IEEE journal on exploratory solid-state computational devices and circuits 10, 82-88 () [10.1109/JXCDC.2024.3482464]  GO OpenAccess  Download fulltext Files BibTeX | EndNote: XML, Text | RIS

http://join2-wiki.gsi.de/foswiki/pub/Main/Artwork/join2_logo100x88.png Journal Article  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;
CVD graphene contacts for lateral heterostructure MoS2 field effect transistors
npj 2D materials and applications 8(1), 35 () [10.1038/s41699-024-00471-y]  GO OpenAccess  Download fulltext Files BibTeX | EndNote: XML, Text | RIS

All known publications ...
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 Record created 2024-12-11, last modified 2025-08-09


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