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Validating a DFT Strategy’s Detection Capability regarding Emerging Faults in RRAMs

; ;

In
Proceedings of the 2021 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) : VLSI : virtual conference - 4-8 October 2021, Singapore, Nanyang Technological University Center / conference general co-chairs: Anupam Chattopadhyay (Nanyang Technological University, Singapore) and Andrea Calimera (Politecnico di Torino, Italy); publisher: IEEE

Konferenz/Event:IFIP/IEEE 29. International Conference on Very Large Scale Integration , online , VLSI-SoC , 2021-10-04 - 2021-10-08

ImpressumPiscataway, NJ : IEEE

ISBN978-1-6654-2614-5, 978-1-6654-2615-2

Online
DOI: 10.1109/VLSI-SoC53125.2021.9606993


Einrichtungen

  1. Lehrstuhl für Integrierte digitale Systeme und Schaltungsentwurf (611110)



Dokumenttyp
Contribution to a book/Contribution to a conference proceedings

Format
online, print

Sprache
English

Anmerkung
Peer reviewed article

Externe Identnummern
SCOPUS: SCOPUS:2-s2.0-85122923779
WOS Core Collection: WOS:000814059800016

Interne Identnummern
RWTH-2022-05412
Datensatz-ID: 847520

Beteiligte Länder
Germany

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The record appears in these collections:
Document types > Events > Contributions to a conference proceedings
Document types > Books > Contributions to a book
Faculty of Electrical Engineering and Information Technology (Fac.6)
Documents in print
Public records
611110
 Record created 2022-05-30, last modified 2025-12-23
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